1. Field of the Invention
The present invention relates to a gate driver generating scan signals in a display device, and more particularly to a shift register in a gate driver, which operates with a reduced number of external bus lines, and a display device employing such a shift register.
2. Description of the Related Art
Image display devices, such as liquid crystal display devices, are generally equipped with a gate driver using a tape carrier package (TCP), a chip on glass (COG), etc. In such display devices, however, there have been difficulties in improving design effectiveness and reducing manufacturing cost of the gate driver circuit and the display devices.
To alleviate such difficulties, there haven been developments such as the gate driving technology without having a gate driver IC (integrated circuit). In other words, a display device has a gate driving part which is not installed in the form of an IC on a display panel but is integrally formed at a portion of a display panel. The structure of such gate driving part is called “gate-IC-less structure” in this description. In the gate-IC-less structure, amorphous silicon thin film transistors (a-Si TFTs) are generally used. Examples of a-Si TFT can be found in U.S. Pat. No. 5,517,542 and commonly assigned Korean Patent Application No. 2002-3398 (or Korean Laid Open Publication No. 2002-66962). The conventional gate driving part with the gate-IC-less structure includes one or more shift registers to provide scan signals to a display panel.
FIG. 1 is a circuit diagram illustrating a unit stage of a conventional shift register. Referring to FIG. 1, the stage 100 of a conventional shift register includes a pull-up part 110, a pull-down part 120, a pull-up driving part 130, and a pull-down driving part 140. The stage 100 generates a gate signal (or scan signal) in response to a scan start signal STV or an output signal of a previous stage. In case that the stage 100 is the first stage of a shift register, the stage 100 receives the scan start signal STV to output the gate signal. In contrast, in case that the stage 100 is not the first stage of a shift register, the stage 100 receives a gate signal generated from a previous stage to output the gate signal. A shift register having such stage(s) is mounted on a TFT panel of a display device.
FIG. 2 is a block diagram illustrating a conventional shift register including multiple stages as shown in FIG. 1. Referring to FIGS. 1 and 2, the shift register 174 has ‘N’ stages SRC1-SRCN for generating ‘N’ gate signals (or scan signals) GOUT1-GOUTN, respectively, and a dummy stage SRCN+1 for providing a control signal to the previous stage. The stages SRC1-SRCN each receive first and second clock signals CKV, CKVB, high and ground level voltages VDD, VSS as gate turn-on and -off voltages VON, VOFF, and a control signal from an output of the next stage.
In particular, the first stage receives a scan start signal STV in addition to the above mentioned signals to output the first gate signal GOUT1 for selecting the first gate line. The first gate signal GOUT1 is also provided to an input terminal IN of the second stage. The second stage SRC2 receives the first gate signal GOUT1 from the first stage in addition to the above mentioned signals to output the second gate signal GOUT2 for selecting the second gate line. The second gate signal GOUT2 is also provided to an input terminal IN of the third stage SRC3. In like manner, the N-th stage SRCN receives the (N−1)-th gate signal from an (N−1)-th stage and a control signal from the dummy stage SRCN+1 in addition to the other clock and voltage signals to output the N-th gate signal GOUTN for selecting N-th gate line.
FIG. 3 is a graphical view of signal waveforms of the shift register in FIG. 1. Referring to FIGS. 1-3, a stage in the shift register 174 receives the first or second clock signal CKV/CKVB, that is, the odd numbered ones of the stages receive the first clock signal CKV, and the even numbered ones receive the second clock signal CKVB that has an inverted phase with respect to the first clock signal CKV. The shift register 174 generates the gate signals to the gate lines of a TFT substrate in sequence. The first and second clock signals CKV, CKVB are obtained from an output signal of a timing controller (not shown). Generally, the output signal of the timing controller has an amplitude in the range from 0V to 3V and is amplified to be in the range from −8V to 24V to drive a-Si TFT. The first and second clock signals use the amplified output signal.
As described above, a conventional shift register having the gate-IC-less structure with a-Si transistor requires at least five bus lines: a bus line for transferring the scan start signal STV that is a start signal in a horizontal direction, a bus line for transferring the first clock signal CKV to apply the gate off voltage, which is connected to odd numbered gate lines, a bus line for transferring the second clock signal CKVB to apply the gate off voltage, which is connected to even numbered gate lines, and bus lines for providing the high and ground level voltages VDD, VSS to each of the stages. The five bus lines are connected to a gate driver region of a display panel via a dummy pin of TCP having source driver IC mounted thereon, or the five bus lines are attached on the display panel to be connected to the gate driver region.
However, the conventional shift registers have problems including the followings. A separate space for forming a jumper that transfers signals and power to each of the stages is required. Especially, in a liquid crystal display panel having a narrow bezel an increased effective display region, the space for the bus lines is more limited. Also, when the five or more bus lines are formed via TCP or FPC, a dummy space of the TCP and a width of the FPC are increased so that the manufacturing cost increases and the space for the bus lines is more limited. Further, when the a-Si transistor is used for a gate driver circuit, the a-Si transistor may be damaged in DC bias state such as the gate on and off voltages VON, VOFF. As a result, the a-Si transistor malfunctions. Furthermore, the a-Si transistor needs a large voltage difference such as −14V to 20V, so that metal pads of the display panel may be damaged due to the large voltage difference. Especially, when the display panel is subjected to a high temperature and humidity, the metal pads may be eroded or undesirable electric paths may be formed between the metal pads due to the humidity.